During circuit switching, transient currents can cause power supply collapse on very large scale integration (VLSI) devices. As current discharges, decoupling capacitance and the power distribution network may have difficulty supplying sufficient current. A current supply collapse may cause logic delay increase or other functional faults in the device. Typically in clocked circuits, the positive clock edge will arrive and cause a wave of activity and a corresponding current spike at each clock cycle. The current spike may create a voltage sag and prevent reliable operation of the target device.
FIG. 1a illustrates an exemplary logic circuit that represents an abstraction of a system implemented on a target device. As shown, a single inverter drives node N with equal capacitive loads C1 and C2. The nominal reference terminals for C1 and C2 are Vdd and ground respectively. The capacitive loads, C1 and C2, may be derived from logic and wire and metal capacitance, and shield wires on the target device. Also shown is inductance between the power supply and on-die circuits. As shown in FIG. 1b a rising transition on the load N causes C2 to charge through the power supply path, and a falling transition on N causes C1 to charge through the power supply path. A rising transition on N causes only internal power dissipation of the charge in C1, which does not affect the power supply. Similarly, a falling transition on N only causes internal power dissipation of the charge in C2.
FIG. 2a illustrates a clock pulse. FIG. 2b illustrates the current waveform associated with logic on the device. As shown, the logic on a device typically has a large amount of activity shortly after a positive clock edge. The clock edge causes the flip-flops to switch and a subsequent wave of activity propagates through the combinatorial logic. FIG. 2c illustrates the current waveform associated with a clock network. As shown, the clock network exhibits a current waveform with two narrow spikes at the positive and negative edges of the clock waveform. This leads to a pair of unequal voltage transients at each clock edge as illustrated in FIG. 2d. 
In the past, designers added decoupling capacitance on the device to address this problem. The decoupling capacitance required, however, would often need to be several times larger than the capacitive load on the original design. In addition to adding to the cost of the design, the decoupling capacitance had to be built in between Vdd and ground and required a large amount of area, which was undesirable.
Prior approaches used to address clock current did not rely on the details of the relationship of the clock current waveforms to the details of the power distribution network. The analysis in FIGS. 1a-b and 2a-d show the details of how a logic transition to a voltage that is the same as the opposite terminal in the parasitic capacitcance causes current that flows completely within the integrated circuit, and therefore does not cause any transient current external to this chip. Since most of the power supply impedance lies off chip, this is the primary source of voltage noise on the chip. In contrast, prior approaches did not distinguish between on-chip and off chip currents. Therefore they considered all current created during a clocking transient to be important, neglecting the significant difference between on-chip and off-chip current. Furthermore these treatments did not consider the possibility of the parasitic clock capacitance to be distributed between Gnd and Vdd, but assumed that it was all connected to Gnd.